1. Field of the Invention
The present invention relates to a field effect transistor and a method of fabricating the same, and more particularly, to a field effect transistor having a hyperfine channel length and an excellent electrical characteristic, and a method of fabricating the same.
2. Discussion of Related Art
In order to realize the high integration of a semiconductor device, technology for forming a fine pattern should be developed prior thereto. Currently, an E-beam lithography method, an extreme ultraviolet (EUV) exposure method, an X-ray exposure method, etc. are used for fabricating a channel of a nanometer scale, so that expensive equipment is needed. Therefore, production cost increases, and mass production is restricted.
As the semiconductor device is highly integrated, the performance thereof is deteriorated due to size reduction. In particular, in the case of a metal insulator semiconductor (MOS) device that occupies most of the semiconductor devices, there arise many problems because the channel length, the junction depth of a source and a drain, and the thickness of a gate insulating layer are decreased. That is, in the conventional semiconductor device, the source and the drain are formed by a self-aligning method after forming the gate insulating layer and a gate electrode. Hence, concentration and distribution of impurity ions contained in the source and the drain may not be freely adjusted, so that the conventional semiconductor device is susceptible to a short channel effect such as a drain induced barrier lowering (DIBL) effect, and an increase of a gate induced drain leakage current (GIDL) due to overlap between the gate and the source or between the gate and the drain when the length of the gate is reduced. Further, an annealing process for activating impurity ions injected into the source and the drain is performed in the state that the gate insulating layer is formed, so that temperature adjustment for the annealing process is restricted.
To solve these problems, there has been recently proposed a replacement gate structure. However, a fabrication process thereof is very complicated, and there is a difficulty in forming the source and the drain using the self-aligning method. Accordingly, there is needed a new fabrication method which can solve the foregoing problems and fabricate a semiconductor device having high integration density and high performance.